1. Field of the Invention
The present invention relates generally to the testing of semiconductor chips. More particularly, the present invention relates to measuring internal clock skew to determine whether the clock skew is within a given specification.
2. Description of the Related Art
Digital circuits typically include digital components that operate in synchronism. In such systems, clocks are utilized to synchronize events between digital components such as flip-flops, multiplexers, adders, and multipliers. A clock generates a series of sequential square wave pulse signals that transition from a low state (i.e., logical xe2x80x9c0xe2x80x9d) to a high state (i.e., logical xe2x80x9c1xe2x80x9d). The series of pulses, also known as a pulse train, is sent by the clock through conductive lines to each of the digital components to indicate when specific events must be performed.
Digital circuits are typically triggered by the xe2x80x9cactivexe2x80x9d edge of a clock cycle. The active edge is typically the rising edge of the square wave pulse, although it may sometimes be on the falling edge of the pulse. A digital circuit usually requires its various components to be synchronized with active edges of the clock cycles to function properly. Therefore, it is intended that all clocks within the digital circuit are synchronized. However, factors such as the routing direction and the position of the clock source relative to the digital component may cause a delay. The difference in time between clock signal edges is known as clock skew. If a chip has an excessive clock skew (beyond a certain tolerance set by design specifications), the chip may fail.
To maximize what gets accomplished during every clock cycle, chips are designed with minimal margin of error. However, the margin of error must include the clock skew present in the chip. Because chip speeds continue to improve, the margin of error before chip failure is growing smaller and smaller. Therefore, clock skew continues to occupy an increasingly greater percentage of clock cycle time despite sophisticated clock distribution schemes to minimize clock skew. The clock skew problem is compounded by the need to generate and distribute multiple clocks, such as clocks used to operate the I/O, bus, and core logic in many digital systems.
Complex digital circuits must undergo extensive operability testing because the presence of even one defective gate or transistor may compromise the reliability or even the functionality of the chip. Therefore, chips must be tested to determine whether clock skew is within the limits set by the chip specification. The information is then used to identify defective parts during manufacturing sort and production testing. The measuring of clock skew is also useful during silicon xe2x80x9cdebugxe2x80x9d, and may shorten the time required to take the chip from first tape-out to high volume manufacturing.
One conventional method of measuring clock skew is known as tester probing, in which a production tester makes physical contact with the chip to test for various characteristics. However, production testers add significant economic cost (e.g., a tester may cost several million dollars) and production time to the chip manufacturing process. Furthermore, if additional tester pins are required, there may be appreciable extra cost as well, particularly because a larger integrated circuit package may be needed to accommodate the chip.
Another problem with production testers is that they cannot operate at the frequency of the fastest chips. The current maximum operating frequency for production testers is about 400 Mhz, while the fastest chips currently operate at about 800 Mhz. As chip complexity increases, it becomes more and more necessary to have built in self-test circuitry, such as a boundary scan chain system or JTAG (joint test action group, IEEEstd 1149.1), which uses scan registers to capture state from device input and output pins.
FIG. 1 is a block diagram of a boundary scan chain system 10 for testing a chip 11 as known in the art. Boundary scan chain system 10 includes a chip 11 that has a number of scan chain elements 12a-d that are coupled to a test clock (tclk). Data is entered serially into chip 11 from a data signal line 14 to scan chain element 12a on the active edge of the cycle of the tclk. The data is then shifted through the other scan chain elements 12b-d on each tclk pulse. Each scan chain element 12a-d performs a testing operation on the data. The data then exits chip 11 and boundary scan chain system 10 through data signal line 16. A detailed description of a boundary scan chain may be found in 1149.1-1990 Test Access Port and Boundary-Scan Architecture from The Institute of Electrical and Electronics Engineers (IEEE).
In view of the foregoing, it is desirable to have a method and apparatus for measuring internal clock skew within the boundary chain scan process to avoid the cost and production time associated with tester probing and having additional test pins.
According to an embodiment of the present invention, an integrated circuit for measuring internal clock skew is provided. The integrated circuit includes a first controlled delay module, which is operable to receive one of a sampling clock signal and a sampled clock signal. The integrated circuit further includes a first flip-flop having a first input coupled to the first controlled delay module and a second input coupled to one of the sampling clock signal and said sampled clock signal. The first flip-flop is operable to generate an output based on skew between the sampled clock signal and the sampling clock signal.